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2/3/4/6英寸SiC晶片产品标准

2 inch diameter Silicon Carbide (SiC) Substrate Specification

等级 Grade工业级Production研究级Research Grade试片级Dummy Grade
直径Diameter50.8 mm±0.38 mm
厚度Thickness330 μm±25μm
晶片方向Wafer OrientationOn axis :<0001>±0.5°for 4H-N/6H-N/4H-SI/6H-SI
Off axis : 4.0°toward(11
2-0) ±0.5° for 4H-N
微管密度Micropipe Density≤5 cm-2≤15 cm-2≤50 cm-2
电阻率Resistivity4H-N0.015~0.028 Ω·cm
6H-N0.02~0.1 Ω·cm(90%) >1E5 Ω·cm
4/6H-SI>1E5 Ω·cm
主定位边方向  Primary Flat{10-10}±5.0°
主定位边长度Primary Flat Length15.9 mm±1.7 mm
次定位边长度  Secondary Flat Length8.0 mm±1.7 mm
次定位边方向Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
边缘 Edge exclusion1 mm
总厚度变化/弯曲度/翘曲度 TTV/Bow /Warp≤15μm /≤25μm /≤25μm
表面粗糙度RoughnessPolish   Ra≤1 nm
CMP    Ra≤0.5 nm

裂纹(强光灯观测) # Cracks by high intensity light

NoneNone1 allowed, ≤1 mm

六方空洞(强光灯观测)* Hex Plates by high intensity light

Cumulative area≤1 %Cumulative area≤1 %Cumulative area≤3 %

多型(强光灯观测)* Poly type Areas by high intensity light

NoneCumulative area≤2 %Cumulative area≤5%

划痕(强光灯观测)*& Scratches by high intensity light

3 scratches to 

1×wafer diameter 

cumulative length

5 scratches to 

1×wafer diameter  

cumulative length

8 scratches to 

1×wafer diameter  

cumulative length

崩边#Edge chipNone

3 allowed, ≤0.5 mm each

5 allowed, ≤1 mm each

表面污染物(强光灯观测)Contamination by high intensity

light

None


Notes:
* Defects limits apply to entire wafer surface except for the edge exclusion area.
# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.


3 inch diameter Silicon Carbide (SiC) Substrate Specification

等级 Grade工业级Production研究级Research Grade试片级Dummy Grade
直径Diameter76.2 mm±0.38 mm
厚度Thickness350 μm±25μm
晶片方向Wafer OrientationOn axis :<0001>±0.5°°for 4H- SI 
Off axis : 4.0° toward(11
2-0) ±0.5° for 4H-N
微管密度Micropipe Density≤5 cm-2≤15 cm-2≤50 cm-2
电阻率Resistivity4H-N0.015~0.028 Ω·cm
4H-SI>1E5 Ω·cm(90%) >1E5 Ω·cm
主定位边方向  Primary Flat{10-10}±5.0°
主定位边长度Primary Flat Length22.2 mm±3.2 mm
次定位边长度  Secondary Flat Length11.2 mm±1.5mm
次定位边方向Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
边缘 Edge exclusion2 mm
总厚度变化/弯曲度/翘曲度 TTV/Bow /Warp≤15μm /≤25μm /≤25μm
表面粗糙度RoughnessPolish   Ra≤1 nm
CMP   Ra≤0.5 nm
裂纹(强光灯观测) # Cracks by high intensity lightNone1 allowed, ≤1 mm1 allowed, ≤2mm

六方空洞(强光灯观测)* Hex Plates by high intensity light

Cumulative area≤1 %Cumulative area≤1 %Cumulative area≤3 %

多型(强光灯观测)* Poly type Areas by high intensity light

NoneCumulative area≤2 %Cumulative area≤5%

划痕(强光灯观测)*& Scratches by high intensity light

3 scratches to 

1×wafer diameter 

cumulative length

5 scratches to 

1×wafer diameter 

 cumulative length

8 scratches to 

2×wafer diameter  

cumulative length

崩边#Edge chipNone

3 allowed, ≤0.5 mm each

5 allowed, ≤1 mm each

表面污染物(强光灯观测)Contamination by high intensity

light

None


Notes:

 * Defects limits apply to entire wafer surface except for the edge exclusion area.

# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.



4 inch diameter Silicon Carbide (SiC) Substrate Specification

等级 Grade

Z级Zero MPD

工业级Production

研究级Research Grade

试片级Dummy Grade

直径Diameter100.0 mm±0.5 mm
厚度Thickness4H-N350 μm±25μm
4H-SI500 μm±25μm
晶片方向Wafer OrientationOff axis : 4.0° toward(112-0) ±0.5° for 4H-N
On axis :<0001>±0.5°°for 4H- SI
微管密度Micropipe Density≤1 cm-2≤5 cm-2≤15 cm-2≤50 cm-2
电阻率Resistivity4H-N0.015~0.028 Ω·cm
6H-N0.02~0.1 Ω·cm(90%) >1E5 Ω·cm
4/6H-SI>1E5 Ω·cm
主定位边方向Primary Flat{10-10}±5.0°
主定位边长度Primary Flat Length32.5 mm±2.0 mm
次定位边长度Secondary Flat Length18.0 mm±2.0mm
次定位边方向Secondary Flat OrientationSilicon face up: 90° CW. from Prime flat ±5.0°
边缘 Edge exclusion3 mm
总厚度变化/弯曲度/翘曲度 TTV/Bow /Warp≤15μm /≤25μm /≤40μm
表面粗糙度RoughnessPolish   Ra≤1 nm
CMP    Ra≤0.5 nm

裂纹(强光灯观测) # Cracks by high 

intensity light

None1 allowed, ≤2 mm

Cumulative length≤10mm, 

single length≤2mm

六方空洞(强光灯观测)* Hex Plates by high 

intensity light

Cumulative area≤1 %

Cumulative 

a≤1 %

Cumulative 

area3 %

多型(强光灯观测)* Poly type Areas by high

intensity light

None

Cumulative

 area≤2%

Cumulative 

area≤5%

划痕(强光灯观测)*& Scratches by high 

intensity light

3 scratches to 

1×wafer diameter

cumulative length

5 scratches to

1×wafer diameter

cumulative length

5 scratches to 

1×wafer diameter

cumulative length

崩边#Edge chipNone

3 allowed, 

≤0.5mm each

5 allowed, 

≤1 mm each

表面污染物(强光灯观测) Contamination by 

high intensity light

None


Notes:

* Defects limits apply to entire wafer surface except for the edge exclusion area.

# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.


6inch diameter Silicon Carbide (SiC) Substrate Specification

等级 Grade

Z级Zero MPD

工业级Production

研究级Research Grade

试片级Dummy Grade

直径Diameter150.0 mm±0.5 mm

厚度Thickness

4H-N350 μm±25μm
4H-SI500 μm±25μm
晶片方向Wafer Orientation

Off axis : 4.0° toward(112(-)0) ±0.5° for 4H-N

On axis : <0001>±0.5°°for 4H- SI
电阻率Resistivity4H-N0.015~0.028 Ω·cm
4H-SI>1E5 Ω·cm(90%) >1E5 Ω·cm
主定位边方向Primary Flat{10-10}±5.0°
主定位边长度Primary Flat Length47.5 mm±2.5 mm 
边缘Edge exclusion3 mm

总厚度变化/弯曲度/翘曲度TTV/Bow /Warp

≤15μm /≤25μm /≤40μm
表面粗糙度RoughnessPolish   Ra≤1 nm
CMP    Ra≤0.5 nm

裂纹(强光灯观测) # Cracks by high 

intensity light

None1 allowed, ≤2 mm

Cumulative length≤10mm, 

single length≤2mm

六方空洞(强光灯观测)* Hex Plates by high 

intensity light

Cumulative area≤1 %

Cumulative

 area≤1 %

Cumulative

 area≤3 %

多型(强光灯观测)* Polytype Areas by high 

intensity light

None

Cumulative

 area≤2 %

Cumulative 

area≤5%

划痕(强光灯观测)*& Scratches by high 

intensity light

3 scratches to 

1×wafer diameter     

cumulative length

5 scratches to

1×wafer diameter

cumulative length 

5 scratches to 

1×wafer diameter

cumulative length

崩边#Edge chip

None

3 allowed, 

≤0.5 mm each 

5 allowed, 

≤1 mm each

表面污染物(强光灯观测) Contamination by 

high intensity light

None


Notes:

* Defects limits apply to entire wafer surface except for the edge exclusion area.

# Defects shall be existed in the edge area, only defect beyond of the prescribed scope could be considered as reject cause. & the scratches should be checked on Si face only.